1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a circuit for outputting data of a semiconductor memory apparatus that does not use a delay locked loop (DLL) circuit.
2. Related Art
In general, semiconductor memory apparatuses output stored data in synchronization with a clock.
FIG. 1 is a block diagram illustrating a circuit for outputting data of a semiconductor memory apparatus according to the related art.
A data clock generating unit 10 generates a data clock CLK_data according to a data input/output mode that is provided by a semiconductor memory apparatus.
For example, if a semiconductor memory apparatus may be DDR (a double data rate) type device, that is a data input/output mode in which four data are input and output at one time, the data clock generating unit 10 generates a data clock CLK_data for two cycles in response to one read command. The DDR outputs data when the data clock rises and falls.
A clock synchronizing unit 20 receives the data clock CLK_data and data DATA, synchronizes the data DATA with the data clock CLK_data, and outputs the data DATA synchronized with the data clock CLK_data as output data DATA_out.
However, an output timing of the output data DATA_out becomes earlier or later than the data clock according to a change in an external voltage VDD level. When the output timing of the output data DATA_out is changed, an external system that receives the output data DATA_out of the semiconductor memory apparatus cannot recognize the output DATA_out properly. This problem becomes serious when an operating speed of the semiconductor memory apparatus that does not use the DLL circuit increases.